ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
, V
DDQ
= 2.5V ~ 2.7V
Auto & Self refresh
7.8us refresh interval (64ms refresh period, 8K cycle)
SSTL-2 I/O interface
66pin TSOPII package
M13S5121632A
8M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Ordering information:
PRODUCT ID
M13S5121632A -5TG
MAX FREQ
200MHz
VDD
2.5V
PACKAGE
TSOPII
COMMENTS
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
1/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
