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M13S64322A 参数 Datasheet PDF下载

M13S64322A图片预览
型号: M13S64322A
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32位×4银行双数据速率同步DRAM [512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 49 页 / 819 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
Revision History
Revision 0.5 (May 03, 2007)
- Delete BGA ball name of packing dimensions
Preliminary
M13S64322A
Revision 0.4 (May 14,2002)
- Change AC Parameters
Revision
Version
tRC
tRP
-4
13 tCK
4 tCK
Rev. 0.3
-5
11 tCK
3 tCK
-4
14 tCK
20 ns
Rev. 0.4
-5
12 tCK
20 ns
Revision 0.3 (December 13,2001)
- The Max / Min value of D, D1, E, E1 (LQFP 100L PKG outline dimension) are added.
Revision 0.2 (Agu 31,2001)
- Changed DC Current
Revision
Version
IDD4R
IDD5
-4
330
305
Rev. 0.1
-5
-
260
-4
385
350
Rev. 0.2
-5
-
285
Revision
IDD6
CKE
≦0.2
Rev. 0.1
CKE≦0.2, t
CK
=∞
2.5mA
Rev. 0.2
2.5mA
7mA
CKE≦0.2, t
CK
= t
CK
(min)
- Added 144 Ball FBGA Pin arrangement.
- Added BGA 144B Package Outline.
Revision 0.1 (April 11,2001)
- Original
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 0.5
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