ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2, 2.5, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.3V ~ 2.7V, V
DDQ
= 2.3V ~ 2.7V
Auto & Self refresh
64ms refresh period, 4K cycle
SSTL-2 I/O interface
66pin TSOPII and 60 ball BGA package
M13S64164A
1M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Ordering Information:
PRODUCT NO.
M13S64164A -5TG
M13S64164A -6TG
M13S64164A -5BG
M13S64164A -6BG
MAX FREQ
200MHz
166MHz
200MHz
166MHz
2.5V
BGA
V
DD
2.5V
PACKAGE
66TSOPII
COMMENTS
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.4
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