ESMT
DDR II SDRAM
Features
JEDEC Standard
V
DD
= 1.8V ± 0.1V, V
DDQ
= 1.8V ± 0.1V
Internal pipelined double-data-rate architecture; two data access per clock cycle
M14D2561616A
4M x 16 Bit x 4 Banks
DDR II SDRAM
Bi-directional differential data strobe (DQS, /DQS); /DQS can be disabled for single-ended data strobe operation.
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 3, 4, 5, 6
Additive Latency: 0, 1, 2, 3, 4
Burst Type : Sequential and Interleave
Burst Length : 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READ; center-aligned with data for WRITE
Data mask (DM) for write masking only
Off-Chip-Driver (OCD) impedance adjustment
On-Die-Termination for better signal quality
Special function support
-
-
50/ 75/ 150 ohm ODT
High Temperature Self refresh rate enable
Auto & Self refresh
Refresh cycle :
-
-
8192 cycles/64ms (7.8μs refresh interval) at 0
℃ ≦
T
C
≦ +85 ℃
8192 cycles/32ms (3.9μs refresh interval) at
+85 ℃ ＜
T
C
≦
+95
℃
SSTL_18 interface
84-ball BGA package
Ordering Information:
PRODUCT NO.
MAX FREQ
V
DD
Data rate
(CL-tRCD-tRP)
DDR2-800 (5-5-5)
DDR2-800 (6-6-6)
DDR2-667 (5-5-5)
BGA
Pb-free
PACKAGE
COMMENTS
M14D2561616A -2.5BG
M14D2561616A -3BG
400MHz
333MHz
1.8V
1.8V
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
1/59
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
