ESMT
PSRAM
Features
• Wide voltage range: 2.7V–3.6V
• Access Time: 55 ns, 70 ns
• Ultra-low active power
— Typical active current: 1mA @ f = 1 MHz
— Typical active current: 14 mA @ f = fmax (For 55-ns)
—Typical active current: 8 mA @ f = fmax (For 70-ns)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
M24L216128SA
2-Mbit (128K x 16)
Pseudo Static RAM
when both Byte High Enable and Byte Low Enable are
disabled (
BHE
,
BLE
HIGH), or during a write operation
( CE LOW and
WE
LOW).
Writing to the device is accomplished by asserting Chip
Enable ( CE LOW) and Write Enable (
WE
) input LOW. If
Byte Low Enable (
BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
16
). If Byte High Enable (
BHE
) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written
into the location specified on the address pins (A
0
through
A
16
).
Reading from the device is accomplished by asserting Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable (
WE
) HIGH. If Byte Low Enable
(
BLE
) is LOW, then data from the memory location specified
by the address pins will appear on I/O
0
to I/O
7
. If Byte High
Enable(
BHE
) is LOW, then data from memory will appear on
I/O
8
to I/O
15
. Refer to the truth table for a complete description
of read and write modes.
Functional Description
The M24L216128SA is a high-performance CMOS Pseudo
Static RAM organized as 128K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both
BHE
and
BLE
are HIGH).
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the chip is deselected ( CE
HIGH), or when the outputs are disabled (
OE
HIGH), or
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2008
Revision
:
1.2
1/14
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
