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M24L48512DA-60BIG 参数 Datasheet PDF下载

M24L48512DA-60BIG图片预览
型号: M24L48512DA-60BIG
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K ×8 )伪静态RAM [4-Mbit (512K x 8) Pseudo Static RAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 12 页 / 278 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
PSRAM
M24L48512DA
4-Mbit (512K x 8)
Pseudo Static RAM
Features
Advanced low power architecture
High speed: 55 ns, 60 ns and 70 ns
Wide voltage range: 2.7V to 3.6V
Typical active current: 1mA @ f = 1 MHz
Low standby power
Automatic power-down when deselected
Enable (
WE
)inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O
0
through I/O
15
) is then
written into the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by asserting the
Chip Enable One ( CE1 ) and Output Enable ( OE ) inputs LOW
while forcing Write Enable (
WE
) HIGH and Chip Enable
Two(CE2) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected CE1
HIGH or CE2 LOW), the outputs are disabled ( OE HIGH), or
during write operation ( CE1 LOW, CE2 HIGH, and
WE
LOW).See the Truth Table for a complete description of read
and write modes.
Functional Description
The M24L48512DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 8 bits. Easy
memory expansion is provided by an active LOW Chip
Enable( CE1 ), an active HIGH Chip Enable (CE2), and active
LOW Output Enable ( OE ).This device has an automatic
power-down feature that reduces power consumption
dramatically when deselected. Writing to the device is
accomplished by taking Chip Enable One ( CE1 ) and Write
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2008
Revision
:
1.1
1/12