ESMT
PSRAM
M24L48512SA
4-Mbit (512K x 8)
Pseudo Static RAM
Features
•
•
•
•
•
•
Advanced low power architecture
High speed: 55 ns, 60 ns and 70 ns
Wide voltage range: 2.7V to 3.6V
Typical active current: 1mA @ f = 1 MHz
Low standby power
Automatic power-down when deselected
consumption dramatically when deselected. Writing to the
device is accomplished by taking Chip Enable ( CE ) and Write
Enable (
WE
) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
18
).Reading from the device is
accomplished by asserting the Chip Enable ( CE ) and Output
Enable ( OE ) inputs LOW while forcing Write Enable (
WE
)
HIGH . Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O
pins. The eight input/output pins (I/O
0
through I/O
7
) are placed
in a high-impedance state when the device is deselected ( CE
HIGH), the outputs are disabled ( OE HIGH), or during write
operation ( CE LOW and
WE
LOW). See the Truth Table
for a complete description of read and write modes.
Functional Description
The M24L48512SA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 8 bits. Easy
memory expansion is provided by an active LOW Chip
Enable( CE ) and active LOW Output Enable ( OE ).This device
has an automatic power-down feature that reduces power
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2008
Revision
:
1.1
1/12
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
