ESMT
PSRAM
Features
‧Advanced
low-power architecture
• High speed: 55 ns, 70 ns
• Wide voltage range: 2.7V to 3.6V
• Typical active current: 2 mA @ f = 1 MHz
• Typical active current: 11 mA @ f = f
MAX
• Low standby power
• Automatic power-down when deselected
M24L816512SA
8-Mbit (512K x 16)
Pseudo Static RAM
Byte Low Enable are disabled (
BHE
,
BLE
HIGH), or during
a write operation ( CE LOW and
WE
LOW).
Writing to the device is accomplished by taking Chip
Enable( CE LOW) and Write Enable (
WE
) input LOW. If
Byte Low Enable (
BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is written into the location specified on the
address pins(A
0
through A
18
). If Byte High Enable (
BHE
) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written
into the location specified on the address pins (A
0
through
A
18
).
Reading from the device is accomplished by taking Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable (
WE
) HIGH. If Byte Low Enable
(
BLE
) is LOW, then data from the memory location specified
by the address pins will appear on I/O
0
to I/O
7
. If Byte High
Enable(
BHE
) is LOW, then data from memory will appear on
I/O
8
toI/O
15
. Refer to the truth table for a complete description
of read and write modes.
Functional Description
The M24L816512SA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both
BHE
and
BLE
are HIGH).
The input/output pins (I/O0through I/O
15
) are placed in a
high-impedance state when : deselected ( CE
HIGH),
outputs are disabled (
OE
HIGH), both Byte High Enable
and
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2009
Revision
:
1.5
1/14
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
