ESMT
M52D32321A
Page Read Cycle at Different Bank @ Burst Length=4
0
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CLOCK
CKE
HIGH
*Note1
CS
RAS
CAS
ADDR
BA
*Note2
RAa
CAc
CAa
CBd
RBb
CBb
CAe
RAa
A10/AP
CL=2
RBb
QAa0 QAa1
QAa3
QAa2
QBb1
QBb0
QAa2
QBb0
QAa3
QBb2
QBb1
QBb3 QAc0
QBd1 QAe0
QAc1 QBd0
QAe1
DQ
CL=3
QAa0 QAa1
QBb2
QBb3 QAc0
QBd1 QAe0
QAc1 QBd0
QAe1
WE
DQM
Read
(B-Bank)
Read
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
: Don't care
*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2009
Revision : 1.6 16/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
