ESMT
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V
±
0.2V,T
A
= 0 °C ~ 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
VDDQ
M52S16161A
Value
0.9 x V
DDQ
/ 0.2
0.5 x V
DDQ
tr / tf = 1 / 1
0.5 x V
DDQ
See Fig.2
Unit
V
V
ns
V
Vtt =0.5x VDDQ
500
50
Output
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
500
30 pF
Output
Z0=50
20 pF
(Fig.1) DC Output Load circuit
(Fig.2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Symbol
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
Number of valid output data
CAS latency=2
CAS latency=1
56
1
2
1
1
2
1
0
ea
4
Version
-8
16
24
20
40
100
70
-10
20
30
20
50
Unit
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
1
2
2
2
3
Note
1
1
1
1
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2.
Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.5
5/29
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
