ESMT
Mobile SDRAM
M52S32162A
1M x 16Bit x 2Banks
Mobile Synchronous DRAM
FEATURES
2.5V power supply
LVCMOS compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
CAS Latency (1, 2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
Special Function Support.
-
PASR (Partial Array Self Refresh )
-
TCSR (Temperature compensated Self Refresh)
-
DS (Driver Strength)
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M52S32162A is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 x 1,048,576 words by 16
bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Product ID
M52S32162A -6TG
Max
Freq.
Package
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
166MHz 54 Pin TSOP(II)
M52S32162A -7.5TG 133MHz 54 Pin TSOP(II)
M52S32162A -10TG
M52S32162A -6BG
100MHz 54 Pin TSOP(II)
166MHz
54 Ball VFBGA
54 Ball VFBGA
54 Ball VFBGA
M52S32162A -7.5BG 133MHz
M52S32162A -10BG
100MHz
PIN CONFIGURATION (TOP VIEW)
TOP View
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
NC
BA
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ1 5
V
S SQ
DQ1 4
DQ1 3
V
DDQ
DQ1 2
DQ1 1
V
S SQ
DQ1 0
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
54 Ball FVBGA(8mmx8mm)
1
A
B
C
D
E
F
G
H
J
V
S S
DQ14
DQ12
2
D Q1 5
D Q1 3
DQ11
3
V
S S Q
4
5
6
7
V
DDQ
8
DQ0
DQ2
DQ4
DQ6
9
V
DD
DQ1
V
DDQ
V
SS Q
V
DDQ
V
S S Q
V
DDQ
V
S SQ
DQ3
DQ5
DQ10
DQ9
DQ8
NC
CLK
A11
V
SS
V
DD
LDQM
DQ7
WE
CS
A1 0
V
DD
UDQM
CKE
A9
CAS
BA
A0
A9
RAS
NC
NC
A8
V
SS
A7
A5
A6
A4
A1
A2
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Dec. 2008
Revision
:
1.4
1/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
