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M53D128168A_1 参数 Datasheet PDF下载

M53D128168A_1图片预览
型号: M53D128168A_1
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4银行移动DDR SDRAM [2M x 16 Bit x 4 Banks Mobile DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 46 页 / 1076 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
Mobile DDR SDRAM
M53D128168A
Operation Temperature Condition -40°C~85°C
2M x 16 Bit x 4 Banks
Mobile
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data
access per clock cycle
Bi-directional data strobe (DQS)
No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK )
Quad bank operation
CAS Latency : 2, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
Special function support
-
PASR (Partial Array Self Refresh)
-
Internal TCSR (Temperature Compensated Self
Refresh)
-
DS (Driver Strength)
All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
Data mask (DM) for write masking only
V
DD
/V
DDQ
= 1.7V ~ 1.9V
Auto & Self refresh
15.6us refresh interval (64ms refresh period, 4K cycle)
1.8V LVCMOS-compatible inputs
60 ball BGA package
Ordering information :
Part NO.
M53D128168A -7.5BAIG
M53D128168A -10BAIG
MAX FREQ
133MHz
100MHz
VDD
1.8V
PACKAGE
8x13 mm
BGA
COMMENTS
Pb-free
Pb-free
Functional Block Diagram
CLK
CLK
CKE
Address
Mode Register &
Extended Mode
Register
Clock
Generator
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
DQS
Sense Amplifier
DM
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
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