ESMT
Mode Register Definition
Mode Register Set (MRS)
M53D128168A
Operation Temperature Condition -40°C~85°C
The mode register stores the data for controlling the various operating modes of Mobile DDR SDRAM. It programs CAS
latency, addressing mode, burst length and various vendor specific options to make Mobile DDR SDRAM useful for variety of
different applications. The default value of the register is not defined, therefore the mode register must be written in the power up
sequence of Mobile DDR SDRAM. The mode register is written by asserting low on CS , RAS , CAS ,
WE
and BA0 (The
Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of
address pins A0~A11 in the same cycle as CS , RAS , CAS ,
WE
and BA0 going low is written in the mode register. Two clock
cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is
divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read
latency from column address) uses A4~A6. A7~A11 is used for test mode. A7~A11 must be set to low for normal MRS operation.
Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
BA1
BA0
A11~ A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
RFU*
CAS Latency
BT
Burst Length
Mode Register
A3
0
1
Burst Type
Sequential
Interleave
Burst Length
CAS Latency
BA1 BA0
0
0
1
0
Operating Mode
MRS Cycle
EMRS Cycle
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserve
Reserve
2
3
Reserve
Reserve
Reserve
Reserve
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Latency
Sequential Interleave
Reserve
Reserve
2
2
4
4
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
* RFU should stay “0” during MRS cycle
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
10/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
