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MC74VHC1GT00DFT1 参数 Datasheet PDF下载

MC74VHC1GT00DFT1图片预览
型号: MC74VHC1GT00DFT1
PDF下载: 下载PDF文件 查看货源
内容描述: 2输入与非门/ CMOS逻辑电平转换器与LSTTL兼容输入 [2-Input NAND Gate / CMOS Logic Level Shifter with LSTTL-Compatible Inputs]
分类和应用: 转换器电平转换器
文件页数/大小: 4 页 / 577 K
品牌: ETL [ E-TECH ELECTRONICS LTD ]
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2–Input NAND Gate / CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
MC74VHC1GT00
The MC74VHC1GT00 is a single gate 2–input NAND fabricated with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power
supply.
The MC74VHC1GT00 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT00 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when
V
CC
= 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
High Speed: t
PD
= 3.1 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
=
2mA
(Max) at T
A
= 25°C
TTL–Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
CMOS–Compatible Outputs: V
OH
> 0.8 V
CC
; V
OL
< 0.1
V
CC
@Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic
Families
Chip Complexity: FETs = 64; Equivalent Gates = 14
MARKING DIAGRAMS
5
4
1
2
3
VH
d
SC–70/SC–88A/SOT–353
DF SUFFIX
CASE 419A
Pin 1
d = Date Code
4
Y
5
Figure 1. Pinout
(Top View)
1
2
3
VH
d
Figure 2. Logic Symbol
Pin 1
d = Date Code
SOT–23/TSOP–5/SC–59
DT SUFFIX
CASE 483
FUNCTION TABLE
PIN ASSIGNMENT
1
2
3
4
5
IN B
IN A
GND
OUT Y
V
CC
A
L
L
H
H
Inputs
B
L
H
L
H
Output
Y
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 4 of this data sheet.
VHT0–1/4