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EM636165TS-6I/6IG 参数 Datasheet PDF下载

EM636165TS-6I/6IG图片预览
型号: EM636165TS-6I/6IG
PDF下载: 下载PDF文件 查看货源
内容描述: 1Mega ×16同步DRAM (SDRAM)的 [1Mega x 16 Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器
文件页数/大小: 73 页 / 756 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech
Features
Fast access time: 5/5.5/6.5/7.5 ns
Fast clock rate: 166/143/125/100 MHz
Self refresh mode: standard and low power
Internal pipelined architecture
512K word x 16-bit x 2-bank
Programmable Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Individual byte controlled by LDQM and UDQM
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V
±
0.3V power supply
Interface: LVTTL
50-pin 400 mil plastic TSOP II package
Lead Free Package available
EM636165-XXI
Preliminary (Rev. 1.1, 04/2005)
1Mega x 16 Synchronous DRAM (SDRAM)
Pin Assignment (Top View)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE#
CAS#
RAS#
CS#
A11
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
Key Specifications
EM636165
t
CK3
t
RAS
t
AC3
t
RC
Clock Cycle time(min.)
Row Active time(max.)
Access time from CLK(max.)
Row Cycle time(min.)
-6I/7I/8I/10I
6/7/8/10ns
36/42/48/60 ns
5/5.5/6.5/7.5 ns
54/63/72/90 ns
Ordering Information
Industrial Operating temperature: -40~85°C
Part Number
EM636165TS-6I/6IG
EM636165TS-7I/7IG
EM636165TS-8I/8IG
Frequency
166MHz
143MHz
125MHz
Package
TSOP II
TSOP II
TSOP II
TSOP II
EM636165TS-10I/10IG
100MHz
G : indicates Lead Free Package
Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured
as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command
which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a
programmable mode register, the system can choose the most suitable modes to maximize its performance. These
Etron Technology, Inc.
No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.