EM636165TS-8 参数 Datasheet PDF下载

EtronTech

6

1M x 16 SDRAM

EM636165

Write and AutoPrecharge command (refer to the following figure)

(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address)

The Write and AutoPrecharge command performs the precharge operation automatically after

the write operation. Once this command is given, any subsequent command can not occur within a

time delay of { (burst length -1) + t

WR

+ t

RP

(min.) } . At full-page burst, only the write operation is

performed in this command and the auto precharge function is ignored.

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

Bank A

Activate

Write A

AutoPrecharge

COMM AND

NOP

NOP

NOP

NOP

NOP

NOP

NOP

t

DAL

CAS# latency=1

tCK1, DQ's

CAS# latency=2

tCK2, DQ's

CAS# latency=3

tCK3, DQ's

DIN A0

DIN A1

*

t

DAL

DIN A0

DIN A1

*

t

DAL

DIN A0

DIN A1

t

DAL

=

t

WR

+

t

RP

*

*

Begin AutoPrecharge

Bank can be reactivated at completion of

t

DAL

Burst Write with Auto-Precharge

(Burst Length = 2, CAS# Latency = 1, 2, 3)

7

Mode Register Set command

(RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data)

The mode register stores the data for controlling the various operating modes of SDRAM. The

Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst

Length in the Mode register to make SDRAM useful for a variety of different applications. The default

values of the Mode Register after power-up are undefined; therefore this command must be issued

at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to

the mode register. One clock cycle is required to complete the write in the mode register (refer to the

following figure). The contents of the mode register can be changed using the same command and

the clock cycle requirements during operation as long as both banks are in the idle state.

Preliminary

11

Rev. 1.8

Nov 2001