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EM636327Q-6 参数 Datasheet PDF下载

EM636327Q-6图片预览
型号: EM636327Q-6
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32高速同步图形DRAM ( SGRAM ) [512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)]
分类和应用: 动态存储器
文件页数/大小: 78 页 / 1387 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM636327  
10 Block Write and AutoPrecharge command  
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "H", BS = Bank, A9 = "H", A3-A7 = Column Address,  
DQ0-DQ31 = Column Mask)  
The Block Write and AutoPrecharge command performs the precharge operation automatically  
after the block write operation. Once this command is given, any subsequent command can not  
occur within a time delay of {tBPL + tRP(min.)}.  
11 Mode Register Set command  
(RAS# = "L", CAS# = "L", WE# = "L", DSF = "L", BS, A0-A9 = Register Data)  
The mode register stores the data for controlling the various operating modes of SGRAM. The  
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst  
Length in the Mode register to make SGRAM useful for a variety of different applications. The  
default values of the Mode Register after power-up are undefined; therefore this command must be  
issued at the power-up sequence. The state of pins A0~A8 and BS in the same cycle is the data  
written to the mode register. One clock cycle is required to complete the write in the mode register  
(refer to the following figure). The contents of the mode register can be changed using the same  
command and the clock cycle requirements during operation as long as both banks are in the idle  
state.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
CLK  
t
CK2  
CKE  
CS#  
Clock min.  
RAS#  
CAS#  
WE#  
DSF  
BS  
A 9  
Address Key  
A0-A8  
DQM  
RP  
t
Hi-Z  
DQ  
Mode Register  
Set Command  
PrechargeAll  
Any  
Command  
Mode Register Set Cycle  
(CAS# Latency = 1, 2, 3)  
Preliminary  
1998  
December  
14