EtronTech
Features
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EM637327
1Mega x 32 SGRAM
Preliminary (08/99)
Pin Assignment (Top View)
DQ29
V
SSQ
DQ30
DQ31
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
DQ0
DQ1
V
SSQ
DQ2
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Fast access time from clock: 4.5/5.5/5.5/6 ns
Fast clock rate: 200/166/143/125 MHz
Fully synchronous operation
Internal pipelined architecture
Dual internal banks (512K x 32bit x 2bank)
Programmable Mode
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
2048 refresh cycles/32ms
Single +3.3V
±
0.3V power supply
Interface: LVTTL
JEDEC 100-pin Plastic package
- QFP (body thickness=2.8mm)
- TQFP1.4 (body thickness=1.4mm)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ 3
V
DDQ
DQ 4
DQ 5
V
SSQ
DQ 6
DQ 7
V
DDQ
DQ16
DQ17
V
SSQ
DQ18
DQ19
V
DDQ
V
DD
V
SS
DQ20
DQ21
V
SSQ
DQ22
DQ23
V
DDQ
DQ M0
DQ M2
WE#
CA S#
RA S#
CS 0#
BS
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ28
V
DDQ
DQ27
DQ26
V
SSQ
DQ25
DQ24
V
DDQ
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
V
SS
V
DD
DQ11
DQ10
V
SSQ
DQ 9
DQ 8
V
DDQ
NC
DQ M3
DQ M1
CL K
CKE
DSF
NC
A8 (AP)
Overview
The EM637327 SGRAM is a high-speed CMOS
synchronous graphics DRAM containing 32 Mbits. It is
internally configured as a dual 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 32 bit banks is organized as 2048 rows by 256
columns by 32 bits. Read and write accesses to the
SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
The EM637327 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth.
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49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A7
A6
A5
A4
V
SS
A10
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
A3
A2
A1
A0
Key Specifications
EM637327
- 5/6/7/8
5/6/7/8 ns
25/30/35/40 ns
4.5/5.5/5.5/6 ns
55/60/63/72 ns
t
CK3
t
RAS
t
AC3
t
RC
Clock Cycle time(min.)
Row Active time(max.)
Access time from CLK(max.)
Row Cycle time(min.)
Ordering Information
Part Number
EM637327Q-5
EM637327TQ-5
EM637327Q-6
EM637327TQ-6
EM637327Q-7
EM637327TQ-7
EM637327Q-8
EM637327TQ-8
Frequency
200 MHz
200 MHz
166 MHz
166 MHz
143 MHz
143 MHz
125 MHz
125 MHz
Package
QFP
TQFP1.4
QFP
TQFP1.4
QFP
TQFP1.4
QFP
TQFP1.4
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
ETRON [ ETRON TECHNOLOGY, INC. ]
