EtronTech
Overview
4M x 32 LPSDRAM
EM669325
The EM669325 SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is
internally configured as a quad 1M x 32 DRAM with a synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 1M x 32 bit banks is organized as 4096 rows by 256
columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which is then followed by a Read or Write command.
The EM669325 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the system can choose the most suitable modes to maximize
its performance. These devices are well suited for applications requiring high memory bandwidth.
Block Diagram
Column
Row Decoder
Decoder
4096 X 256 X 32
CELL ARRAY
(BANK #0)
Sense
Amplifier
CL K
CLO CK
BUFFER
CO N T R OL
S IG N A L
GE N ER A T OR
Sense
Row Decoder
CKE
CS #
RA S#
CA S#
WE#
Amplifier
CO M M A ND
DECODER
MODE
R E G IS T E R
4096X 256 X 32
CELL ARRAY
(BANK #1)
Column
Decoder
CO LU MN
COUN TER
A 1 0 /A P
Column
Row Decoder
Decoder
A0
A9
A10
A11
BA0
BA1
ADDRESS
BUFFER
4096 X 256 X 32
CELL ARRAY
(BANK #2)
Sense
Amplifier
REFRESH
COUN TER
Sense
DQ
BUFFER
DQ 0
D Q31
Row Decoder
Amplifier
4096 X 256 X 32
CELL ARRAY
(BANK #3)
Column
Decoder
Preliminary
│
D Q M 0 ~3
2
Rev 0.6
Sep. 2003
ETRON [ ETRON TECHNOLOGY, INC. ]
