EtronTech
V
SS
Supply
4Mx32 DDR SDRAM
EM6A9320
Ground:
Ground
for the input buffers and core logic
.
Supply
DQ Power:
Provide isolated power to DQs for improved noise immunity.
V
DDQ
Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
V
SSQ
Supply
Reference Voltage for Inputs:
+0.5 x V
DDQ
V
REF
NC
-
No Connect:
These pins should be left unconnected.
Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any
applications using the single ended clocking, apply V
REF
to CK# pin.
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK . Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
Extended Mode Register Set
No-Operation
Device Deselect
Burst Stop
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
State
CKEn-1 CKEn DM BA1 BA0
Idle
(3)
H
X
X
V
V
Any
H
X
X
V
V
Any
H
X
X
X
X
Active
(3)
H
X
V
V
V
H
X
V
V
V
Active
(3)
Active
(3)
H
X
X
V
V
Active
(3)
H
X
X
V
V
Idle
H
X
X
L
L
Idle
H
X
X
L
H
Any
H
X
X
X
X
Any
H
X
X
X
X
Active
(4)
H
X
X
X
X
Idle
H
H
X
X
X
Idle
H
L
X
X
X
Idle
L
H
X
X
X
(Self Refresh)
H
L
X
X
X
A8 A11-A9, A7-0 CS# RAS# CAS# WE#
Row Address
L
L
H
H
L
X
L
L
H
L
H
X
L
L
H
L
L
L
H
L
L
Column
H
L
H
L
L
Address
L
L
H
L
H
A0~A7
H
L
H
L
H
L
L
L
L
OP code
L
L
L
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
H
H
L
X
X
L
L
L
H
X
X
L
L
L
H
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
X
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
Power Down Mode Entry Idle/Active
(5)
Power Down Mode Exit
Any
L
H
X
X
X
(Power Down)
Active
H
X
L
X
X
Data Write/Output
Enable
Active
H
X
H
X
X
Data Mask/Output
Disable
Note:
1. V = Valid data, X = Don't Care, L = Low level, H = High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA0, BA1signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
5
Rev 0.6
May. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
