EtronTech
(V
DD
= 2.5
±
5%, T
A
= 0~70
°C)
Symbol
Parameter
8Mx32 DDR SDRAM
EM6AA320-XXMS
5
Max
Min
Max
Min
6
Max
Unit
Electrical Characteristics and Recommended A.C. Operating Conditions
3.3
Min Max
3.6
Min Max
4
Min
t
CK
t
CH
t
CL
t
DQSCK
t
AC
t
DQSQ
t
RPRE
t
RPST
t
DQSS
t
WPRES
t
WPREH
t
WPST
t
DQSH
t
DQSL
t
IS
t
IH
t
DS
t
DH
t
HP
t
QH
t
RC
t
RFC
t
RAS
t
RCDRD
t
RCDWR
t
RP
t
RRD
tw
R
t
CDLR
t
CCD
t
MRD
t
DAL
t
XSA
t
PDEX
t
REF
Clock cycle time
Clock high level width
Clock low level width
CL = 3
CL = 4
-
3.3
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLMIN
or
tCHMIN
-
10
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
3.6
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLMIN
or
tCHMIN
-
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
4
4
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.45
0.45
tCLMIN
or
tCHMIN
10
10
0.55
0.55
0.7
0.7
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
5
5
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
1.0
1.0
0.5
0.5
tCLMIN
or
tCHMIN
10
10
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
6
-
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.75
0
0.25
0.4
0.35
0.35
1.0
1.0
0.45
0.45
tCLMIN
or
tCHMIN
12
-
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.25
-
-
0.6
-
-
-
-
-
-
-
ns
t
CK
t
CK
ns
ns
ns
t
CK
t
CK
t
CK
ns
ns
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
ns
us
DQS-out access time from CK,CK#
Output access time from CK,CK#
DQS-DQ Skew
Read preamble
Read postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS write postamble
DQS in high level pulse width
DQS in low level pulse width
Address and Control input setup time
Address and Control input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Clock half period
Output DQS valid window
Row cycle time
Refresh row cycle time
Row active time
RAS# to CAS# Delay in Read
RAS# to CAS# Delay in Write
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. Address to Col. Address delay
Mode register set cycle time
Auto precharge write recovery + Precharge
Self refresh exit to read command delay
tHP -
0.35
17
19
12
6
4
5
3
3
2
1
1
9
200
tIS +
2tCK
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
tHP -
0.4
16
18
11
5
3
3
3
3
2
1
1
9
200
tIS +
2tCK
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
tHP -
0.45
15
17
10
5
3
3
3
3
2
1
2
8
200
tIS +
2tCK
-
-
tHP -
0.5
12
14
8
4
2
4
2
2
2
1
2
6
200
tIS +
2tCK
-
-
THP -
0.55
10
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
12
7
3
2
4
2
2
2
1
2
6
200
tIS +
2tCK
-
100K
-
-
-
-
-
-
-
-
-
-
-
7.8
Power down exit time
Refresh interval time
-
7.8
-
7.8
11
Rev 0.7
May. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
