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FHX13X 参数 Datasheet PDF下载

FHX13X图片预览
型号: FHX13X
PDF下载: 下载PDF文件 查看货源
内容描述: 的GaAs FET和HEMT芯片 [GaAs FET & HEMT Chips]
分类和应用: 晶体晶体管放大器
文件页数/大小: 4 页 / 64 K
品牌: EUDYNA [ EUDYNA DEVICES INC ]
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FHX13X, FHX14X
GaAs FET & HEMT Chips
FEATURES
Low Noise Figure: 0.45dB (Typ.)@f=12GHz (FHX13)
High Associated Gain: 13.0dB (Typ.)@f=12GHz
Lg
0.15µm, Wg = 200µm
Gold Gate Metallization for High Reliability
DESCRIPTION
The FHX13X, FHX14X are Super High Electron Mobility Transistor
TM
(SuperHEMT ) intended for general purpose, ultra-low noise and
high gain amplifiers in the 2-18GHz frequency range. The devices
are well suited for telecommunication, DBS, TVRO, VSAT or other
low noise applications.
Fujitsu’s stringent Quality Assurance Program assures the highest
reliability and consistent performance.
ABSOLUTE MAXIMUM RATING (Ambient Temperature Ta=25°C)
Item
Drain-Source Voltage
Gate-Source Voltage
Total Power Dissipation
Storage Temperature
Channel Temperature
*Note:
Mounted on Al2O3 board (30 x 30 x 0.65mm)
Fujitsu recommends the following conditions for the reliable operation of GaAs FETs:
1. The drain-source operating voltage (VDS) should not exceed 2 volts.
2. The forward and reverse gate currents should not exceed 0.2 and -0.05mA respectively with
gate resistance of 4000Ω.
3. The operating channel temperature (Tch) should not exceed 80°C.
Symbol
VDS
VGS
Pt*
Tstg
Tch
Rating
3.5
-3.0
180
-65 to +175
175
Unit
V
V
mW
°C
°C
ELECTRICAL CHARACTERISTICS (Ambient Temperature Ta=25°C)
Item
Saturated Drain Current
Transconductance
Pinch-off Voltage
Gate Source Breakdown Voltage
Noise Figure
FHX13X
Associated Gain
Noise Figure
FHX14X
Associated Gain
Thermal Resistance
Gas
Rth
Channel to Case
Gas
NF
Symbol
IDSS
gm
Vp
VGSO
NF
VDS = 2V
IDS = 10mA
f = 12GHz
Test Conditions
VDS = 2V, VGS = 0V
VDS = 2V, IDS = 10mA
VDS = 2V, IDS = 1mA
IGS = -10µA
Min.
10
35
-0.1
-3.0
-
11.0
-
11.0
-
Limit
Typ. Max.
30
50
-0.7
-
0.45
13.0
0.55
13.0
220
60
-
-1.5
-
0.50
-
0.60
-
300
Unit
mA
mS
V
V
dB
dB
dB
dB
°C/W
Note:
RF parameter sample size 10pcs. criteria (accept/reject)=(2/3)
The chip must be enclosed in a hermetically sealed environment for optimum performance and reliability.
Edition 1.2
July 1999
1