欢迎访问ic37.com |
会员登录 免费注册
发布采购

FLK027XV 参数 Datasheet PDF下载

FLK027XV图片预览
型号: FLK027XV
PDF下载: 下载PDF文件 查看货源
内容描述: 的GaAs FET和HEMT芯片 [GaAs FET & HEMT Chips]
分类和应用: 晶体晶体管
文件页数/大小: 4 页 / 97 K
品牌: EUDYNA [ EUDYNA DEVICES INC ]
 浏览型号FLK027XV的Datasheet PDF文件第2页浏览型号FLK027XV的Datasheet PDF文件第3页浏览型号FLK027XV的Datasheet PDF文件第4页  
FLK027XP, FLK027XV
GaAs FET & HEMT Chips
FEATURES
High Output Power: P1dB = 24.0dBm(Typ.)
High Gain: G1dB = 7.0dB(Typ.)
High PAE:
η
add = 32%(Typ.)
Proven Reliability
Source
Gate
Drain
DESCRIPTION
The FLK027XP, and FLK027XV chip is a power GaAs FET that is
designed for general purpose applications in the Ku-Band frequency
range as it provides superior power, gain, and efficiency.
Fujitsu’s stringent Quality Assurance Program assures the highest
reliability and consistent performance.
Source
ABSOLUTE MAXIMUM RATING (Ambient Temperature Ta=25°C)
Item
Drain-Source Voltage
Gate-Source Voltage
Total Power Dissipation
Storage Temperature
Channel Temperature
Symbol
VDS
VGS
Ptot
Tstg
Tch
Condition
Rating
15
-5
Tc = 25°C
1.88
-65 to +175
175
Unit
V
V
W
°C
°C
Fujitsu recommends the following conditions for the reliable operation of GaAs FETs:
1. The drain-source operating voltage (VDS) should not exceed 10 volts.
2. The forward and reverse gate currents should not exceed 2.2 and -0.1 mA respectively with
gate resistance of 2000Ω.
3. The operating channel temperature (Tch) should not exceed 145°C.
ELECTRICAL CHARACTERISTICS (Ambient Temperature Ta=25°C)
Item
Saturated Drain Current
Transconductance
Pinch-off Voltage
Gate Source Breakdown Voltage
Output Power at 1dB
Gain Compression Point
Power Gain at 1dB
Gain Compression Point
Power-added Efficiency
Thermal Resistance
Symbol
IDSS
gm
Vp
VGSO
P1dB
G1dB
η
add
Rth
Channel to Case
VDS = 10V
IDS
0.6IDSS
f = 14.5GHz
Test Conditions
VDS = 5V, VGS = 0V
VDS = 5V, IDS = 65mA
VDS = 5V, IDS = 5mA
IGS = -5µA
Min.
-
-
-1.0
-5
23
Limit
Typ. Max.
100
50
-2.0
-
24
150
-
-3.5
-
-
Unit
mA
mS
V
V
dBm
6
-
-
7
32
40
-
-
80
dB
%
°C/W
Note:
RF parameter sample size 10pcs. criteria (accept/reject)=(2/3)
The chip must be enclosed in a hermetically sealed environment for optimum performance and reliability.
Edition 1.3
July 1999
1