FLL300IL-1, FLL300IL-2, FLL300IL-3
L-Band Medium & High Power GaAs FET
FEATURES
•
•
•
•
•
High Output Power: P1dB = 44.5dBm (Typ.)
High Gain: G1dB = 12.0dB (Typ.)@1.8GHz (FLL300IL-2)
High PAE:
η
add = 44% (Typ.)
Proven Reliability
Hermetically Sealed Package
DESCRIPTION
The FLL300IL-1, FLL300IL-2, FLL300IL-3 are Power GaAs FETs that are
specifically designed to provide high power at L-Band frequencies with
gain, linearity and efficiency superior to that of silicon devices. The
performance in multitone environments for Class AB operation make
them ideally suited for base station applications.
Fujitsu’s stringent Quality Assurance Program assures the highest
reliability and consistent performance.
ABSOLUTE MAXIMUM RATING (Ambient Temperature Ta=25°C)
Item
Drain-Source Voltage
Gate-Source Voltage
Total Power Dissipation
Storage Temperature
Channel Temperature
Symbol
VDS
VGS
PT
Tstg
Tch
Tc = 25°C
Condition
Rating
15
-5
100
-65 to +175
175
Unit
V
V
W
°C
°C
Fujitsu recommends the following conditions for the reliable operation of GaAs FETs:
1. The drain-source operating voltage (VDS) should not exceed 10 volts.
2. The forward and reverse gate currents should not exceed 80.4 and -17.4 mA respectively with
gate resistance of 25Ω.
3. The operating channel temperature (Tch) should not exceed 145°C.
ELECTRICAL CHARACTERISTICS (Ambient Temperature Ta=25°C)
Item
Saturated Drain Current
Transconductance
Pinch-off Voltage
Symbol
IDSS
gm
Vp
Test Conditions*
VDS = 5V, VGS = 0V
VDS = 5V, IDS = 7200mA
VDS = 5V, IDS = 720mA
f=900MHz
f=1.8GHz
f=2.6GHz
f=900MHz
f=1.8GHz
f=2.6GHz
11.0
10.0
8.0
-
-
-
-
13.0
12.0
10.0
6.0
44
1.1
-
-
-
-
8.0
-
1.5
80
dB
dB
dB
A
%
°C/W
°C
43.0
44.5
-
dBm
Min.
-
-
-1.0
-5
Limit
Typ. Max.
12
16
-
6000
-2.0
-
-3.5
-
Unit
A
mS
V
V
Gate Source Breakdown Voltage
VGSO IGS = -720µA
FLL300IL-1
Output Power
FLL300IL-2
P1dB
at 1dB G.C.P.
VDS = 10V
FLL300IL-3
IDS
=
0.5 IDSS
FLL300IL-1
(Typ.)
Power Gain
FLL300IL-2
G1dB
at 1dB G.C.P.
FLL300IL-3
Drain Current
Power added Efficiency
Thermal Resistance
Channel Temperature Rise
CASE STYLE:
IL
* Under fixed VGS bias condition
Idsr
η
add
Rth
∆T
ch
VDS = 10V
IDS
=
0.5 IDSS (Typ.)
Channel to Case
(10V x Idsr - Pout + Pin) x Rth
G.C.P.: Gain Compression Point
Edition 1.2
July 1999
1
EUDYNA [ EUDYNA DEVICES INC ]
