MP1230A/31A/32A
TIMING DIAGRAM
t
CS
tCH
V
V
IH
50%
50%
CS, BYTE1/BYTE2
IL
t
WR
V
IH
50%
50%
WR
V
V
IL
t
DS
t
DH
IH
50%
50%
DATA BITS
V
IL
t
S
SETTLED TO
+0.01%
I
, I
OUT1 OUT2
IOUT2
:
DAC Current Output 2 Bus.
IOUT2 is a complement of IOUT1
DEFINITION OF CONTROL SIGNALS:
.
CS:
Chip Select.(Active low)
It will enable WR1.
RFB
:
Feedback Resistor.
This internal feedback resistor should always be used
(not an external resistor) since it matches the resistors
in the DAC and tracks these resistors over tempera-
ture.
WR1: Write 1 (Active low)
The WR1 is used to load the digital data bits (DB) into
the input latch.
BYTE1/BYTE2: Byte sequence control.
The BYTE1/BYTE2 control pin is used to select both
MSB and LSB input latches.
VREF
:
Reference Voltage Input.
This input connects an external precision voltage
source to the internal DAC. The VREF can be selected
over the range of +25V to –25V or the analog signal for
a 4-quadrant multiplying mode application.
WR2: Write 2 (Active low)
It will enable XFER.
XFER: Transfer control signal (Active low)
This signal in combination with WR2 causes the 16-bit
data which is available in the input latches to transfer
to the DAC register
VDD
:
Power Supply Voltage.
This is the power supply pin for the part. The VDD can
be from +5 V DC to +15 V DC, however optimum volt-
age is +12 to +15 V DC.
DB0 to DB11: Digital Inputs.
DB0 is the least significant digital input (LSB) and
DB11 is the most significant digital input (MSB).
AGND: Analog Ground
Back gate of the DAC N-channel current steering
IOUT1
:
DAC Current Output 1 Bus.
IOUT1 is a maximum for a digital code of all 1’s in the
DAC register, and is zero for all 0’s in the DAC register.
switches.
DGND: Digital Ground
Rev. 2.00
5
EXAR [ EXAR CORPORATION ]
