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MP1232ABN 参数 Datasheet PDF下载

MP1232ABN图片预览
型号: MP1232ABN
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS微处理器兼容的双缓冲12位数字 - 模拟转换器 [CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter]
分类和应用: 转换器数模转换器微处理器光电二极管
文件页数/大小: 12 页 / 114 K
品牌: EXAR [ EXAR CORPORATION ]
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MP1230A/31A/32A
CMOS Microprocessor Compatible
Double-Buffered 12-Bit
Digital-to-Analog Converter
FEATURES
Superior Ruggedized 1230 Series: 2 KV ESD
Four Quadrant Multiplication
Stable, More Accurate Segmented DAC Approach
– 0.2 ppm/°C Linearity Tempco
– 2 ppm/°C Max Gain Error Tempco
– Lowest Sensitivity to Amplifier Offset
– Lowest Output Capacitance (C
OUT
= 80pF)
– Lower Glitch Energy
Monotonic over Temperature Range
Lower Data Bus Feedthrough @ CS = 1
V
DD
from +11 V to +16 V
Latch-Up Free CMOS Technology
12-Bit Bus Version: MP1208/1209/1210
16-Bit Upgrade: MP7636A
GENERAL DESCRIPTION
The MP1230A series are superior pin for pin replacements
for the 1230 series. The MP1230A series is manufactured using
advanced thin film resistors on a double metal CMOS process
which promotes significant improvements in reliability, latch-up
free performance and ESD protection.
The MP1230A series incorporates a unique decoding tech-
nique yielding lower glitch, higher speed and excellent accuracy
over temperature and time. 12-bit linearity is achieved without
trimming. Outstanding features include:
Stability: integral and differential linearity tempcos are rated
at 0.2 ppm/
°
C typical. Monotonicity is guaranteed over all
temperature ranges. Scale factor tempco is a low 2 ppm/
°
C
maximum.
Low Output Capacitance: Due to smaller MOSFET switch
geometries allowed by decoding, the output capacitance at
I
OUT1
and I
OUT2
is a low 80pF / 40pF and 25pF / 65 pF. This
less than half the competitive DAC 1230 series. Lower ca-
pacitance allows the MP1230A series to achieve settling
times faster than 1
µ
s for a 10 V step.
Low Sensitivity to Output Amplifier Offset: The linearity er-
ror caused by amplifier offset is reduced by a factor of 2 in the
MP1230A series over conventional R-2R DACs.
The MP1230A series uses a circuit which reduces transients
in the supplies caused by DATA bus transitions at CS = 1.
SIMPLIFIED BLOCK DIAGRAM
V
DD
INPUT LATCH
DB11-DB4
DB3-DB0
BYTE1/BYTE2
D
8
8
V
REF
R
FB
V
REF
I
OUT1
I
OUT2
DAC LATCH
D
Q
Q
8
12
LE
LE
D
4
Q
4
12
CS
WR1
LE
XFER WR2 DGND
AGND
Rev. 2.00
1