MP7528
MICROPROCESSOR INTERFACE
A0-A15
A*
V
MA
Address
Decode
Logic
A+1**
DACA/DACB
CS
Address
Decode
Logic
A+1**
MP7528
DAC B
Address Bus
A8-A15
A*
DACA/DACB
CS
DAC A
Address Bus
DAC A
CPU
6800
φ
2
WR
DB0
DB7
MP7528
CPU
8085
WR
ALE
WR
Latch
8212
DB0
DB7
DAC B
D0–D7
Data Bus
AD0–AD7
ADDR/Data Bus
Analog circuitry has been omitted for clarity
*A = Decoded 7528 DAC A Address
**A + 1 = Decoded 7528 DAC B Address
Analog circuitry has been omitted for clarity
*A = Decoded 7528 DAC A Address
**A + 1 = Decoded 7528 DAC B Address
NOTE:
8085 instruction SHLD (store H & L direct) can update
both DACS with data from H and L registers
Figure 2. MP7528 Dual DAC to 6800
CPU Interface
Figure 3. MP7528 Dual DAC to 8085
CPU Interface
PERFORMANCE CHARACTERISTICS
Graph 1. Relative Accuracy vs. Digital Code
5V
Rev. 2.00
9
Graph 2. Relative Accuracy vs. Digital Code
15 V
EXAR [ EXAR CORPORATION ]
