MP7542
ADDRESS BUS VALID
A0 - A1
V
INH
V
INL
t
AWS1
CS
V
INH
V
INL
t
AWS2
WR
t
CWS1
t
AWH
t
CWH
t
WR
t
CWS2
DB3 - DB0
V
INH
V
INL
t
DS
t
DH
DATA
BUS VALID
Figure 1. Timing Diagram
MP7542 Control Inputs
A
1
X
X
0
0
0
0
1
1
1
1
A
0
X
X
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
CS
X
1
WR
X
1
0
CLR
0
1
1
1
1
1
1
1
1
1
Load 12-bit DAC register with data in LOW byte, MIDDLE
byte, & HIGH byte data registers
Load HIGH byte data register on edges as shown
Load MIDDLE byte data register on edges as shown
MP7542 Operation
Resets DAC 12-bit register to code 0000 0000 0000
No operation; device not selected
Load LOW byte data register on edges as shown
Load applicable
data register
with data at
D
0
- D
3
NOTES
1. 1 indicates logic HIGH
2. 0 indicates logic LOW
3. X indicates don’t care
4.
indicates LOW to HIGH transition
5. MSB XXXX XXXX XXXX LSB
high
middle low
byte
byte
byte
6. Although positive-going edge of either CS or WR will load data register, timing is optimized by using WR to
latch data and using CS as a device enable.
Table 1. Truth Table
Rev. 2.00
5
EXAR [ EXAR CORPORATION ]
