MP8798
SIMPLIFIED BLOCK AND TIMING DIAGRAM
AV
DD
DV
DD
Coarse
Comparators
φ
B
V
REF(+)
1/2 R
V
REF(–)
V
REF1(–)
PD
Ladder
4
Adder
5
OFW
CLK
DB9-DB0
OFW
φ
S
N
φ
B
Fine
Resolution
Com-
parators
DFF
6
DB9-DB0
10
N-1
N-1
N
N
CLK
A
IN1
A
IN2
A
IN3
A
IN4
φ
S
1 or 4
MUX
4
WR
2 to 4
Decoder
Latch
A1
A0
AGND DGND
PIN CONFIGURATIONS
See Packaging Section for
Package Dimensions
DB3
DB4
DB5
DB6
DB7
DGND
DV
DD
WR
A1
A0
CLK
DB8
DB9
OFW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB2
DB1
DB0
PD
AV
DD
AGND
A
IN4
A
IN3
A
IN2
A
IN1
1/2 R
V
REF1(–)
V
REF(–)
V
REF(+)
DB3
DB4
DB5
DB6
DB7
DGND
DV
DD
WR
A1
A0
CLK
DB8
DB9
OFW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB2
DB1
DB0
PD
AV
DD
AGND
A
IN4
A
IN3
A
IN2
A
IN1
1/2 R
V
REF1(–)
V
REF(–)
V
REF(+)
28 Pin PDIP (0.300”)
NN28
28 Pin SOIC (Jedec, 0.300”) – S28
28 Pin SSOP – A28
Rev. 3.00
2