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ST16C2552IJ 参数 Datasheet PDF下载

ST16C2552IJ图片预览
型号: ST16C2552IJ
PDF下载: 下载PDF文件 查看货源
内容描述: 具有16字节FIFO 2.97V至5.5V双路UART [2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
文件页数/大小: 35 页 / 356 K
品牌: EXAR [ EXAR CORPORATION ]
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SEPTEMBER 2003
ST16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
REV. 4.2
GENERAL DESCRIPTION
The ST16C2552 (2552) is a dual universal
asynchronous receiver and transmitter (UART). The
ST16C2552 is an improved version of the PC16552
UART. The 2552 provides enhanced UART functions
with 16 byte FIFOs, a modem control interface, and
data rates up to 4 Mbps. Onboard status registers
provide the user with error indications and operational
status.
System interrupts and modem control
features may be tailored by external software to meet
specific user requirements.
Indepedendent
programmable baud rate generators are privded to
select transmit and receive clock rates from 50 Bps to
4 Mbps. The baud rate generator can be configured
for either crystal or external clock input. An internal
loop-back capability allows onboard diagnostics. The
2552 provides block mode data transfers (DMA)
through FIFO controls. DMA transfer monitoring is
provided through the signals TXRDY# and RXRDY#.
An Alternate Function Register provides the user with
the ability to initialize both UARTs concurrently. The
2552 is available in the 44-PLCC package.
FEATURES
Added feature in devices with top marking "A2
YYWW" and newer:
s
5 Volt Tolerant Inputs
Pin-to-pin and functionally compatible to National
PC16552 and Exar’s XR16L2752 and XR16C2852
4 Mbps transmit/receive operation (64 MHz
External Clock Frequency)
2 Independent UART Channels
s
s
Register Set Compatible to 16C550
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable RX FIFO Trigger Levels
Fixed Transmit FIFO interrupt trigger level
Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
s
s
s
s
APPLICATIONS
DMA operation and DMA monitoring via TXRDY#
and RXRDY# pins
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
UART internal register sections A & B may be
written to concurrently
Multi-Function
output allows
functions with few I/O pins
even, odd, or no parity
more
package
Programmable character lengths (5, 6, 7, 8) with
Crystal oscillator or external clock input
F
IGURE
1. ST16C2552 B
LOCK
D
IAGRAM
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDYA#
TXRDYB#
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
3.3V or 5V VCC
GND
UART Channel A
UART
Regs
BRG
8-bit Data
Bus
Interface
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
RXA (or RXIRA)
TXB (or TXIRB)
RXB (or RXIRB)
Crystal Osc/Buffer
Modem Control Logic
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
2552BLK
TXA (or TXIRA)
UART Channel B
(same as Channel A)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Reset
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com