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XR16C850CM 参数 Datasheet PDF下载

XR16C850CM图片预览
型号: XR16C850CM
PDF下载: 下载PDF文件 查看货源
内容描述: 带有128字节FIFO 2.97V至5.5V UART [2.97V TO 5.5V UART WITH 128-BYTE FIFO]
分类和应用: 先进先出芯片
文件页数/大小: 56 页 / 1335 K
品牌: EXAR [ EXAR CORPORATION ]
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xr
REV. 2.3.1
XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
ORDERING INFORMATION
P
ART
N
UMBER
XR16C850CJ
XR16C850CM
XR16C850IJ
XR16C850IM
P
ACKAGE
44-Lead PLCC
48-Lead TQFP
44-Lead PLCC
48-Lead TQFP
O
PERATING
T
EMPERATURE
R
ANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
Active
PIN DESCRIPTIONS
N
OTE
:
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
N
AME
44-P
IN
PLCC
48-P
IN
T
YPE
TQFP
D
ESCRIPTION
I
NTEL
B
US
M
ODE
I
NTERFACE
. T
HE
SEL
PIN IS CONNECTED TO
VCC.
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
29
30
31
2
3
4
5
6
7
8
9
24
26
27
28
43
44
45
46
47
2
3
4
19
I
Address data lines [2:0]. A2:A0 selects internal UART’s configuration registers.
I/O
Data bus lines [7:0] (bidirectional).
I
Input/Output Read (active low). The falling edge instigates an internal read cycle
and retrieves the data byte from an internal register pointed by the address lines
[A2:A0], places it on the data bus to allow the host processor to read it on the lead-
ing edge. Either an active IOR# or IOR is required to transfer data from 850 to CPU
during a read operation. If not used, connect this pin to VCC. Caution:
Input/Output Read (active high). Same as IOR# but active high. Either an active
IOR# or IOR is required to transfer data from 850 to CPU during a read operation.
If not used, connect this pin to GND. During PC Mode, this pin becomes A3. Cau-
tion:
Input/Output Write (active low). The falling edge instigates the internal write cycle
and the rising edge transfers the data byte on the data bus to an internal register
pointed by the address lines [A2:A0]. Either an active IOW# or IOW is required to
transfer data from 850 to the Intel type CPU during a write operation. If not used,
connect this pin to VCC. Caution:
Input/Output Write (active high). The rising edge instigates the internal write cycle
and the falling edge transfers the data byte on the data bus to an internal register
pointed by the address lines [A2:A0]. Either an active IOW# or IOW is required to
transfer data from 850 to the Intel type CPU during a write operation. During PC
Mode, this pin becomes A8. If not used, connect this pin to GND. Caution:
IOR
25
20
I
IOW#
20
16
I
IOW
21
17
I
3