XRD98L63
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
OVDD
OGND
DGND
ADCLK
DVDD
EOS
PBLK
CAL
SBLK
SPIX
CLAMP
FSYNC
AGND
AGND
AVDD
N/C
REFIN
CCDIN
N/C
VCM
AVDD
N/C
AGND
N/C
BIASRES
CAPP
CAPN
AVDD
AGND
OE
RESET
PD
TESTOUT
LOAD
SDI
SCLK
Type
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Digital out
Power
Ground
Ground
Digital in
Power
Digital in
Digital in
Digital in
Digital in
Digital in
Digital in
Digital in
Ground
Ground
Power
Analog
Analog
Analog
Power
Ground
Analog
Analog
Analog
Power
Ground
Digital in
Digital in
Digital in
Digital out
Digital in
Digital in
Digital in
Description
ADC Output (LSB)
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output
ADC Output (MSB)
Digital Output Power Supply (must be < AVDD )
Digital Output Ground
On chip Logic Ground
ADC Clock
On chip Logic Power Supply (must = AVDD)
Even/Odd Line select
Pre-Blanking clock
Calibration Control Clock (clamp OB)
CDS Sample Black Clock
CDS Sample Pixel Clock
DC-Restore Input Clamp Control Clock
Frame Sync Clock
Analog Ground
Analog Ground
Analog Power Supply
(Not used)
CCD Reference Signal
CCD Input Signal
(Not used)
Common mode bias by-pass
Analog Power Supply
(Not used)
Analog Ground
(not used)
External Reference Resistor (connect 18.2KΩ resistor to ground)
ADC Reference By-Pass
ADC Reference By-Pass
Analog Power Supply
Analog Ground
Output Enable Control, 1=high-Z, 0=enable, internal pull down
Reset Control, 1=convert, 0=reset, internal pull up
Power Down Control, 1=Power Down, 0=convert, internal pull down
Factory Test Output
Serial Interface Data Load
Serial Interface Data Input
Serial Interface Shift Clock
Rev.1.01
3
EXAR [ EXAR CORPORATION ]
