XRP7713
Three Channel Digital PWM Step Down Controller
Digital Input/Output Pins (GPIO1-GPIO5) and ENABLE
3.3V CMOS logic compatible, 5V tolerant.
Parameter
Enable Pin Threshold
Input Pin Low Level
Input Pin High Level
Input Pin Leakage Current
Input pin Capacitance
Output Pin Low Level
Output Pin High Level
Output Pin High Level (no load)
2.4
3.3
3.6
5
0.4
2.0
10
Min.
1.08
Typ.
1.14
Max.
1.2
0.8
Units
V
V
V
µA
pF
V
V
V
•
•
•
I
SINK
=1mA
I
SOURCE
=1mA
I
SOURCE
=0mA
•
•
•
V
IO
=3.3V
Conditions
Chip Enable rising threshold
I
2
C Specification
Parameter
I
2
C Speed
Input Pin Low Level, V
IL
Input Pin High Level, V
IH
Hysteresis of Schmitt Trigger
Inputs, V
HYS
Output Pin Low Level (open
drain or collector) V
OL
Input Leakage Current
Output Fall Time from V
IHMIN
to
V
ILMAX
Capacitance for each I/O Pin
Note 3: C
b
is the capacitance of one bus in pF
-10
20+0.1C
b3
2.31
0.165
0.4
10
250
10
Min.
Typ.
Max.
400
1.0
Units
kHz
V
V
V
V
µA
ns
pF
I
SINK
=3mA
Input is between 0.33V and 2.31V
With a bus capacitance from 10pF to
400pF
Conditions
Based upon I
2
C master clock
Gate Drivers
Parameter
GH, GL Rise and Fall Time
GH, GL Pull-up On-State Output
Resistance
GH, GL Pull-down On-State
Output Resistance
GH, GL Pull-down Off-State
Output Resistance
Min.
Typ.
30
6
3
50
Max.
Units
ns
Ω
Ω
kΩ
VIN=VCCD=0V
Conditions
At 10% to 90% of full scale pulse.
1nF C
load
© 2010 Exar Corporation
4/29
Rev. 1.1.1
EXAR [ EXAR CORPORATION ]
