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DECEMBER 2005
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
REV. 1.0.3
GENERAL DESCRIPTION
The XRT75L02 is a two-channel fully integrated Line
Interface Unit (LIU) with Jitter Attenuator for E3/DS3/
STS-1 applications. It incorporates independent
Receivers, Transmitters and Jitter Attenuators in a
single 100 pin TQFP package.
The XRT75L02 can be configured to operate in either
E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84
MHz) modes.The transmitter can be turned off (tri-
stated) for redundancy support and for conserving
power.
The XRT75L02’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L02 incorporates advanced crystal-less
jitter attenuators that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications.
The XRT75L02 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L02 supports local,remote and digital
loop-backs. The XRT75L02 also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
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Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
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On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
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Provides low jitter output clock.
TRANSMITTER:
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Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
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Tri-state Transmit output capability for redundancy
applications
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Transmitters can be turned on or off.
JITTER ATTENUATOR:
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On chip advanced crystal-less Jitter Attenuator.
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Jitter Attenuator can be selected in Receive or
Transmit paths.
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16 or 32 bits selectable FIFO size.
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Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
•
Jitter Attenuators can be disabled.
CONTROL AND DIAGNOSTICS:
•
5 wire Serial Microprocessor Interface for control
and configuration.
•
Supports
Monitoring.
optional
internal
Transmit
Driver
FEATURES
RECEIVER:
•
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
•
Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
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PRBS error counter register to accumulate errors.
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Hardware Mode for control and configuration.
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Supports Local, Remote and Digital Loop-backs.
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Single 3.3 V ± 5% power supply.
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5 V Tolerant I/O.
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Available in 100 pin TQFP.
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-40°C to 85°C Industrial Temperature Range.
APPLICATIONS
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E3/DS3 Access Equipment.
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STS1-SPE to DS3 Mapper.
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DSLAMs.
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Digital Cross Connect Systems.
•
CSU/DSU Equipment.
•
Routers.
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Fiber Optic Terminals.
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Detects and Clears LOS as per G.775.
•
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
•
On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
•
On-chip
clock
synthesizer
generates
the
appropriate rate clock from a single frequency
XTAL.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
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(510) 668-7000
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FAX (510) 668-7017
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www.exar.com
EXAR [ EXAR CORPORATION ]
