XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JUNE 2004
REV. 1.0.0
GENERAL DESCRIPTION
The XRT83L38 is a fully integrated Octal (eight
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100Ω, E1 (2.048Mbps) 75Ω or
120Ω, or J1 110Ω applications.
In long-haul applications the XRT83L38 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.
In T1 applications, the XRT83L38 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as required by FCC rules. It also provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions (The arbitrary pulse generators
are available in both T1 and E1 modes).
The XRT83L38 provides both a parallel
Host
microprocessor interface as well as a
Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip
crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit
path with loop bandwidths of less than 3Hz. The
XRT83L38 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75Ω,
100Ω, 110Ω and 120Ω for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
•
T1 Digital Cross-Connects (DSX-1)
•
ISDN Primary Rate Interface
•
CSU/DSU E1/T1/J1 Interface
•
T1/E1/J1 LAN/WAN Routers
•
Public switching Systems and PBX Interfaces
•
T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
F
IGURE
1 B
LOCK
D
IAGRAM OF THE
XRT83L38 T1/E1/J1 LIU (H
OST
M
ODE
)
MCLKE1
MCLKT1
MASTER CLOCK SYNTHESIZER
MCLKOUT
One of Eight channels, CHANNEL_n - (n= 0:7)
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TAOS
ENABLE
TX FILTER
& PULSE
SHAPER
DFM
DRIVE
MONITOR
LINE
DRIVER
DMO_n
TTIP_n
TRING_n
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
LBO[3:0]
JA
SELECT
QRSS ENABLE
QRSS
DETECTOR
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
LOCAL
ANALOG
LOOPBACK
TXON_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
NETWORK
LOOP
DETECTOR
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
RX
EQUALIZER
RTIP_n
RRING_n
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
RLOS_n
HW/HOST
WR_R/W
RD_DS
ALE_AS
CS
RDY_DTACK
INT
TEST
MICROPROCESSOR CONTROLLER
ICT
µPTS1
µPTS2
D[7:0]
µPCLK
A[7:0]
RESET
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
EXAR [ EXAR CORPORATION ]
