100315 Low Skew Quad Clock Driver
September 1991
Revised November 1999
100315
Low Skew Quad Clock Driver
General Description
The 100315 contains four low skew differential drivers,
designed for generation of multiple, minimum skew differ-
ential clocks from a single differential input. This device
also has the capability to select a secondary single-ended
clock source for use in lower frequency system level test-
ing. The 100315 is a 300 Series redesign of the 100115
clock driver.
Features
s
Low output-to-output skew (≤50 ps)
s
Differential inputs and outputs
s
Secondary clock available for system level testing
s
2000V ESD protection
s
Voltage compensated operating range:
−4.2V
to
−5.7V
Ordering Code:
Order Number
100315SC
Package Number
M16A
Package Descriptions
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Pin Descriptions
Pin Names
CLKIN, CLKIN
CLK
1–4
, CLK
1–4
TCLK
CLKSEL
Description
Differential Clock Inputs
Differential Clock Outputs
Test Clock Input (Note 1)
Clock Input Select (Note 1)
Truth Table
CLKSEL
L
L
H
H
CLKIN
L
H
X
X
CLKIN
H
L
X
X
TCLK
X
X
L
H
CLK
n
L
H
L
H
CLK
n
H
L
H
L
Note 1:
TCLK and CLKSEL are single-ended inputs, with internal 50 kΩ
pull-down resistors.
L
=
LOW Voltage Level
H
=
HIGH Voltage Level
X
=
Don't Care
© 1999 Fairchild Semiconductor Corporation
DS010960
www.fairchildsemi.com
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
