100328
Connection Diagrams
24-Pin DIP/SOIC
Functional Diagram
28-Pin PLCC
Truth Table
OE
L
L
L
H
H
H
H
H
H
DIR
X
L
H
L
L
L
H
H
H
LE
L
H
H
L
L
H
L
L
H
ECL
Port
LOW
(Cut-Off)
Input
LOW
(Cut-Off)
L
H
X
L
H
Latched
L
H
L
H
X
Z
Input
(Note 1)(Note 3)
(Note 2)(Note 3)
(Note 1)(Note 4)
(Note 1)(Note 4)
(Note 2)(Note 4)
(Note 2)(Note 4)
(Note 2)(Note 4)
Note:
LE, DIR, and OE use ECL logic levels
TTL
Port
Z
Notes
Detail
Latched (Note 1)(Note 3)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don’t Care
Z
=
High Impedance
Note 1:
ECL input to TTL output mode.
Note 2:
TTL input to ECL output mode.
Note 3:
Retains data present before LE set HIGH.
Note 4:
Latch is transparent.
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