100329
Logic Symbol
Functional Diagram
Pin Descriptions
Pin Names
E
0
–E
7
T
0
–T
7
OE
CP
DIR
TTL Data I/O
Output Enable Input
Clock Pulse Input (Active Rising Edge)
Direction Control Input
Description
ECL Data I/O
All pins function at 100K ECL levels except for T
0
–T
7
.
Truth Table
OE
L
L
H
H
H
H
H
H
DIR
L
H
L
L
L
H
H
H
CP
X
X
ECL
Port
Input
LOW
(Cut-Off)
L
H
X
L
H
NC
L
H
NC
L
H
X
(Note 1)
(Note 1)
(Note 1)(Note 3)
(Note 2)
(Note 2)
(Note 2)(Note 3)
Note:
DIR and OE use ECL logic levels
TTL
Port
Z
Notes
(Note 1)(Note 3)
Input (Note 2)(Note 3)
L
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don't Care
Z
=
High Impedance
=
LOW-to-HIGH Clock Transition
NC
=
No Change
Detail
Note 1:
ECL input to TTL output mode.
Note 2:
TTL input to ECL output mode.
Note 3:
Retains data present before CP.
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