欢迎访问ic37.com |
会员登录 免费注册
发布采购

100341PC 参数 Datasheet PDF下载

100341PC图片预览
型号: 100341PC
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的8位移位寄存器 [Low Power 8-Bit Shift Register]
分类和应用: 移位寄存器触发器逻辑集成电路光电二极管
文件页数/大小: 9 页 / 97 K
品牌: FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
 浏览型号100341PC的Datasheet PDF文件第1页浏览型号100341PC的Datasheet PDF文件第2页浏览型号100341PC的Datasheet PDF文件第3页浏览型号100341PC的Datasheet PDF文件第4页浏览型号100341PC的Datasheet PDF文件第6页浏览型号100341PC的Datasheet PDF文件第7页浏览型号100341PC的Datasheet PDF文件第8页浏览型号100341PC的Datasheet PDF文件第9页  
Industrial Version  
PLCC DC Electrical Characteristics (Note 7)  
VEE = −4.2V to 5.7V, VCC = VCCA = GND, TC = −40°C to +85°C  
T
C = −40°C  
TC = 0°C to +85°C  
Symbol  
Parameter  
Units  
Conditions  
Loading with  
Min  
Max  
870  
Min  
Max  
870  
VOH  
VOL  
Output HIGH Voltage  
Output LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
1085  
1830  
1095  
1025  
1830  
1035  
mV  
mV  
mV  
mV  
mV  
V
IN = VIH(Max)  
or VIL (Min)  
IN = VIH (Min)  
1575  
1620  
50to 2.0V  
Loading with  
50to 2.0V  
VOHC  
VOLC  
VIH  
V
1565  
870  
1610  
870  
or VIL (Max)  
1170  
1830  
0.50  
1165  
1830  
0.50  
Guaranteed HIGH Signal  
for all Inputs  
VIL  
Input LOW Voltage  
1480  
1475  
mV  
Guaranteed LOW Signal  
for all Inputs  
IIL  
Input LOW Current  
Input HIGH Current  
Power Supply Current  
µA  
µA  
V
IN = VIL (Min)  
IN = VIH (Max)  
IIH  
IEE  
240  
240  
V
Inputs OPEN  
157  
167  
75  
75  
157  
167  
75  
75  
mA  
mA  
V
EE = −4.2V to 4.8V  
EE = −4.2V to 5.7V  
V
Note 7: The specified limits represent the worst casevalue for the parameter. Since these values normally occur at the temperature extremes, additional  
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-  
sen to guarantee operation under worst caseconditions.  
PLCC AC Electrical Characteristics  
VEE = −4.2V to 5.7V, VCC = VCCA = GND  
T
C = −40°C  
T
C = +25°C  
TC = +85°C  
Symbol  
Parameter  
Units  
MHz  
ns  
Conditions  
Min  
Max  
Min  
Max  
Min  
Max  
fMAX  
tPLH  
tPHL  
tTLH  
tTHL  
tS  
Max Clock Frequency  
Propagation Delay  
CP to Output  
425  
425  
425  
Figures 2, 3  
Figures 1, 3  
(Note 8)  
0.90  
0.30  
1.80  
1.90  
1.00  
0.35  
1.80  
1.20  
1.00  
0.35  
1.90  
1.20  
Transition Time  
ns  
ns  
Figures 1, 3  
20% to 80%, 80% to 20%  
Setup Time  
Dn, Pn  
Sn  
0.60  
1.70  
0.90  
0.50  
2.00  
0.55  
1.50  
0.70  
0.50  
2.00  
0.55  
1.50  
0.70  
0.50  
2.00  
Figure 4  
Figure 3  
tH  
Hold Time  
Dn, Pn  
Sn  
ns  
tPW(H)  
Pulse Width HIGH  
CP  
ns  
Note 8: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.  
5
www.fairchildsemi.com