100350 Low Power Hex D-Type Latch
July 1988
Revised August 2000
100350
Low Power Hex D-Type Latch
General Description
The 100350 contains six D-type latches with true and com-
plement outputs, a pair of common Enables (E
a
and E
b
),
and a common Master Reset (MR). A Q output follows its D
input when both E
a
and E
b
are LOW. When either E
a
or E
b
(or both) are HIGH, a latch stores the last valid data
present on its D input before E
a
or E
b
went HIGH. The MR
input overrides all other inputs and makes the Q outputs
LOW. All inputs have 50 k
Ω
pull-down resistors.
Features
s
20% power reduction of the 100150
s
2000V ESD protection
s
Pin/function compatible with 100150
s
Voltage compensated operating range
= −
4.2V to
−
5.7V
Ordering Code:
Order Number
100350PC
100350QC
Package Number
N24E
V28A
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
28-Pin PLCC
Pin Names
D
0
–D
5
E
a
, E
b
MR
Q
0
–Q
5
Q
0
–Q
5
Data Inputs
Common Enable Inputs (Active LOW)
Asynchronous Master Reset Input
Data Outputs
Complementary Data Outputs
Description
© 2000 Fairchild Semiconductor Corporation
DS009884
www.fairchildsemi.com
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
