100353 Low Power 8-Bit Register
July 1988
Revised August 2000
100353
Low Power 8-Bit Register
General Description
The 100353 contains eight D-type edge triggered, master/
slave flip-flops with individual inputs (D
n
), true outputs (Q
n
),
a clock input (CP), and a common clock enable pin (CEN).
Data enters the master when CP is LOW and transfers to
the slave when CP goes HIGH. When the CEN input goes
HIGH it overrides all other inputs, disables the clock, and
the Q outputs maintain the last state.
The 100353 output drivers are designed to drive 50
Ω
termi-
nation to
−
2.0V. All inputs have 50 k
Ω
pull-down resistors.
Features
s
Low power operation
s
2000V ESD protection
s
Voltage compensated operating range
= −
4.2V to
−
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Order Number
100353PC
100353QC
100353QI
Package Number
N24E
V28A
V28A
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−
40
°
C to
+
85
°
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
D
0
–D
7
CEN
CP
Q
0
–Q
7
NC
Data Inputs
Clock Enable Input
Clock Input (Active Rising Edge)
Data Outputs
No Connect
Description
28-Pin PLCC
© 2000 Fairchild Semiconductor Corporation
DS009882
www.fairchildsemi.com
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
