100355 Low Power Quad Multiplexer/Latch
July 1989
Revised August 2000
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of
which can accept and store data from two sources. When
both Enable (E
n
) inputs are LOW, the data that appears at
an output is controlled by the Select (S
n
) inputs, as shown
in the Operating Mode table. In addition to routing data
from either D
0
or D
1
, the Select inputs can force the out-
puts LOW for the case where the latch is transparent (both
Enables are LOW) and can steer a HIGH signal from either
D
0
or D
1
to an output. The Select inputs can be tied
together for applications requiring only that data be steered
from either D
0
or D
1
. A positive-going signal on either
Enable input latches the outputs. A HIGH signal on the
Master Reset (MR) input overrides all the other inputs and
forces the Q outputs LOW. All inputs have 50 k
Ω
pull-down
resistors.
Features
s
Greater than 40% power reduction of the 100155
s
2000V ESD protection
s
Pin/function compatible with 100155
s
Voltage compensated operating range
= −
4.2V to
−
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Order Number
100355PC
100355QC
100355QI
Package Number
N24E
V28A
V28A
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−
40
°
C to
+
85
°
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
E
1
, E
2
S
0
, S
1
MR
D
na
–D
nd
Q
a
–Q
d
Q
a
–Q
d
Description
Enable Inputs (Active LOW)
Select Inputs
Master Reset
Data Inputs
Data Outputs
Complementary Data Outputs
28-Pin PLCC
© 2000 Fairchild Semiconductor Corporation
DS010147
www.fairchildsemi.com
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
