100360 Low Power Dual Parity Checker/Generator
March 1998
Revised August 2000
100360
Low Power Dual Parity Checker/Generator
General Description
The 100360 is a dual parity checker/generator. Each half
has nine inputs; the output is HIGH when an even number
of inputs are HIGH. One of the nine inputs (I
a
or I
b
) has the
shorter through-put delay and is therefore preferred as the
expansion input for generating parity for 16 or more bits.
The 100360 also has a Compare (C) output which allows
the circuit to compare two 8-bit words. The C output is
LOW when the two words match, bit for bit. All inputs have
50 k
Ω
pull-down resistors.
Features
s
Lower power than 100160
s
2000V ESD protection
s
Pin/function compatible with 100160
s
Voltage compensated operating range
= −
4.2V to
−
5.7V
s
Min to Max propagation delay 35% tighter than 100160
s
Available to industrial grade temperature range
Ordering Code:
Order Number
100360PC
100360QC
100360QI
Package Number
N24E
V28A
V28A
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−
40
°
C to
+
85
°
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP
Pin Descriptions
Pin Names
I
a
, I
b
, I
na
, I
nb
Z
a
, Z
b
C
Description
Data Inputs
Parity Odd Outputs
Compare Output
Truth Table
(Each Half)
Sum of
HIGH Inputs
Even
Odd
Output
Z
HIGH
LOW
28-Pin PLCC
Comparator Function
C
=
(I
0a
⊕
I
1a
)
+
(I
2a
⊕
I
3a
)
+
(I
4a
⊕
I
5a
)
+
(I
6a
⊕
I
7a
)
+
(I
0b
⊕
I
1b
)
+
(I
2b
⊕
I
3b
)
+
(I
4b
⊕
I
5b
)
+
(I
6b
⊕
I
7b
)
© 2000 Fairchild Semiconductor Corporation
DS010611
www.fairchildsemi.com
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