Logic Symbol
Pin Descriptions
Pin Names
Description
ECL Data I/O
Complementary ECL
E0–E3
E0–E3
Data I/O
T0–T3
OE
TTL Data I/O
Output Enable Input Levels
Latch Enable Input Levels
Direction Control
Connection Diagrams
LE
DIR
24-Pin DIP
Input (TTL levels)
GNDECL
GNDECLO
GNDS
ECL Ground
ECL Output Ground
ECL Ground-to-Substrate
ECL Quiescent Power Supply
ECL Dynamic Power Supply
TTL Quiescent Ground
TTL Dynamic Ground
TTL Quiescent Power Supply
TTL Dynamic Power Supply
VEE
VEED
GNDTTL
GNDTTLD
VTTL
VTTLD
Truth Table
LE
DIR
OE
ECL
Port
TTL
Port
Z
28-Pin PLCC
Notes
0
0
0
LOW
(Cut-Off)
0
0
0
1
1
0
Input Output (Note 1)(Note 4)
LOW
Z
(Cut-Off)
0
1
1
1
1
0
0
1
1
0
1
0
Output Input (Note 2)(Note 4)
Input
Latched
Low
Z
X
(Note 1)(Note 3)
(Note 1)(Note 3)
Input (Note 2)(Note 3)
(Cut-Off)
Latched
1
1
1
X
(Note 2)(Note 3)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
Note 1: ECL input to TTL output mode.
Note 2: TTL input to ECL output mode.
Note 3: Retains data present before LE set HIGH.
Note 4: Latch is transparent.
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