100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer
January 2003
Revised January 2003
100LVEL11
3.3V ECL 1:2 Differential Fanout Buffer
General Description
The 100LVEL11 is a low voltage 1:2 differential fanout
buffer. One differential input signal is fanned out to two
identical differential outputs. By supplying a constant refer-
ence level to one input pin a single ended input condition is
created.
With inputs Open or both inputs at V
EE
, the differential Q
outputs default LOW and Q outputs default HIGH.
The 100 series is temperature compensated.
Features
s
Typical propagation delay of 330 ps
s
Typical I
EE
of 24 mA
s
Typical skew of 5 ps between outputs
s
Internal pull-down resistors on D
s
Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
s
Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up tests
s
Moisture Sensitivity Level 1
s
ESD Performance:
Human Body Model
>
2000V
Machine Model
>
200V
Ordering Code:
Package
Order Number
100LVEL11M
100LVEL11M8
(Preliminary)
Number
M08A
MA08D
Product
Code
Top Mark
KVL11
KV11
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Package Description
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Diagram
Top View
Pin Descriptions
Pin Name
Q
0
, Q
0
, Q
1
, Q
1
D, D
V
CC
V
EE
Description
ECL Data Outputs
ECL Data Inputs
Positive Supply
Negative Supply
© 2003 Fairchild Semiconductor Corporation
DS500775
www.fairchildsemi.com
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
