DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver
August 1986
Revised March 2000
DM74LS244
Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description
These buffers/line drivers are designed to improve both the
performance and PC board density of 3-STATE buffers/
drivers employed as memory-address drivers, clock driv-
ers, and bus-oriented transmitters/receivers. Featuring 400
mV of hysteresis at each low current PNP data line input,
they provide improved noise rejection and high fanout out-
puts and can be used to drive terminated lines down to
133Ω.
Features
s
3-STATE outputs drive bus lines directly
s
PNP inputs reduce DC loading on bus lines
s
Hysteresis at data inputs improves noise margins
s
Typical I
OL
(sink current)
24 mA
s
Typical I
OH
(source current)
−15
mA
s
Typical propagation delay times
Inverting
Noninverting
10.5 ns
12 ns
18 ns
s
Typical enable/disable time
Inverting
Noninverting
130 mW
135 mW
s
Typical power dissipation (enabled)
Ordering Code:
Order Number
DM74LS244WM
DM74LS244SJ
DM74LS244N
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
G
L
L
H
L
=
LOW Logic Level
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
Z
=
High Impedance
Output
A
L
H
X
Y
L
H
Z
© 2000 Fairchild Semiconductor Corporation
DS008442
www.fairchildsemi.com
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