FM93C66A 4K-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Timing Diagrams
SYNCHRONOUS DATA TIMING
CS
t
CSS
t
SKH
t
SKL
t
CSH
SK
t
DIS
DI
t
DIH
Valid
Input
t
PD
DO (Data Read)
t
SV
DO (Status Read)
Valid Status
t
DH
Valid
Output
t
PD
Valid
Output
t
DF
t
DF
Valid
Input
READ CYCLE (READ)
t
CS
CS
SK
DI
1
Star t
Bit
1
0
A
n
A
n-1
A1
Address
Bits(8/9)
A0
Opcode
Bits(2)
DO
High - Z
D u m my
Bit
9 3 C 6 6 A ( O R G = 1 ;
A
n
=A7; D
n
=D15
) :
Address bits pattern -> A7-A6-A5-A4-A3-A2-A1-A0; User defined
9 3 C 6 6 A ( O R G = 0 ;
A
n
=A8; D
n
=D7
) :
Address bits pattern -> A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
;;;
;;;
0
D
n
D1
D0
WRITE ENABLE CYCLE (WEN)
t
CS
CS
SK
DI
1
Start
Bit
0
0
A
n
A
n-1
A1
Address
Bits(8/9)
A0
Opcode
Bits(2)
DO
High - Z
93C66A (ORG=1;
A
n
=A7
):
Address bits pattern -> 1-1-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1)
93C66A (ORG=0;
A
n
=A8
):
Address bits pattern -> 1-1-x-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1)
8
FM93C66A Rev. B.1
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FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
