October 1997
FDV302P
Digital FET, P-Channel
General Description
This P-Channel logic level enhancement mode field effect
transistor is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage
applications as a replacement for digital transistors. Since
bias resistors are not required, this one P-channel FET can
replace several digital transistors with different bias resistors
such as the DTCx and DCDx series.
Features
-25 V, -0.12 A continuous, -0.5 A Peak.
R
DS(ON)
= 13
Ω
@ V
GS
= -2.7 V
R
DS(ON)
= 10
Ω
@ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Compact industry standard SOT-23 surface mount
package.
Replace many PNP digital transistors (DTCx and DCDx)
with one DMOS FET.
SOT-23
Mark:302
SuperSOT -6
TM
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
ESD
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current
T
A
= 25
o
C unless otherwise noted
FDV302P
-25
-8
Units
V
V
A
- Continuous
- Pulsed
-0.12
-0.5
0.35
-55 to 150
6.0
Maximum Power Dissipation
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
W
°C
kV
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient
357
°C/W
© 1997 Fairchild Semiconductor Corporation
FDV302P REV. F
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
