PRODUCT SPECIFICATION
ML4824
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 5 shows a leading
edge control scheme.
One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary “no-load” period, thus lowering ripple
voltage generated by the switching action. With such
synchronized switching, the ripple voltage of the first stage
is reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
L1
+
DC
I1
VIN
SW2
I2
I3
I4
SW1
C1
RL
RAMP
VEAO
REF
U3
+
EA
–
DFF
RAMP
OSC
U4
CLK
+
–
U1
R
Q
D U2
Q
CLK
VSW1
TIME
TIME
Figure 4. Typical Trailing Edge Control Scheme.
L1
+
DC
I1
VIN
SW2
I2
I3
I4
SW1
C1
RL
RAMP
VEAO
U3
+
EA
–
REF
VEAO
+
–
CMP
U1
DFF
R
Q
D U2
Q
CLK
VSW1
TIME
RAMP
OSC
U4
CLK
TIME
Figure 5. Typical Leading Edge Control Scheme.
REV. 1.0.6 11/7/03
11
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
