MC81F4x16
22.1 Registers
ADMR
A/D MODE REGISTER
00BDH
7
6
5
4
3
2
1
0
SSBIT
EOC
ADCLK
ADCH
ADMR
Reset value: 00H
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
After reset, the start/stop bit is turned off. You can select only one analog input channel at a time.
Other analog input (AD0-AD14,BGR) can be selected dynamically by manipulating the ADCH. And
the pins not used for analog input can be used for normal I/O function.
0: Stop operation
SSBIT
EOC
Start or Stop bit
1: Start operation
0: Conversion not complete
1: Conversion complete
End of Conversion
A/D Clock Selection
00: fxx/1
01: fxx/2
10: fxx/4
11: fxx/8
ADCLK
0000: AN0
0001: AN1
0010: AN2
0011: AN3
0100: AN4
0101: AN5
0110: AN6
0111: AN7
1000: AN8
1001: AN9
1010: AN10
1011: AN11
1100: AN12
1101: AN13
1110: AN14
1111: BGR
ADCH
A/D Input Pin Selection
ADDRH
A/D CONVERTER DATA HIGH REGISTER
00BEH
7
6
5
4
3
2
1
0
.11
.10
.9
.8
.7
.6
R
.5
.4
ADDRH
Reset value: XXH
R
R
R
R
R
R
R
A 8-bit data register for higher 8-bits of the 12-bit ADC result.
ADDRL
A/D CONVERTER DATA LOW REGISTER
00BFH
7
6
5
4
3
-
2
-
1
-
0
-
.3
.2
.1
.0
ADDRL
Reset value: X-H
R
R
R
R
R
R
R
R
A 8-bit data register for lower 4-bits of the 12-bit ADC result.
October 19, 2009 Ver.1.35
145
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